1. Technical Field
A circuit for generating a column select (Yi) control signal in a memory device is disclosed. More particularly, a circuit for generating a column select (Yi) control signal in a memory device is disclosed that can be widely used in a memory device, etc. that performs a page mode in order to speed up a read/write speed, among the memory devices.
2. Description of the Related Art
There are several modes to speed up the read/write speed of data in memory devices.
Recently, among the memory devices that have been developed for a mobile phone, there is a memory device having the page read mode for improving the read speed. However, there is no memory device having the page write mode for improving the write speed. Thus, there is a need for a structure that can generate a Yi control signal that operates in the page write mode corresponding to the page read mode.
In the common memory device, a row address is used to select a specific word line of a plurality of word lines. If the word line is thus selected, data in the memory cell is charge-shared in the bit line. A bit line sense amplifier amplifies the narrow signal that was charge-shared to a level having a full swing width. This state is called an active state and this path is called a row path.
Further, a column address is used to select one of the plurality of the memory cells connected to the specific word line selected by the row address and to output data in the bit line to the outside. This path is called a column path. In general, when comparing the row path and the column path, the row path is longer. Lots of time is thus consumed in the row path.
Therefore, in order to perform more efficient read or write operations in the memory device, the concept of the page mode was developed. The page mode means the memory cells sharing the same word line. There are 4 words, 8 words, 16 words, a full page, and the like, depending on the length along which the page operation is performed by the memory cells sharing the same word line. As the memory cells share the same word line, the row address is same but the column address is different.
Therefore, the row path operation and the column path operation are not performed every time when data is stored at or written in the memory cells. Instead, the operation of the row path having the longer path is performed once when it is performed at the first time. Thus, only the column address is changed in a state that the word line is selected, so that the column path operation can be performed at high speed.
A conventional circuit for generating a column select (Yi) control signal operating in a normal operation mode will be described. FIG. 1a is the circuit diagram for generating the Yi control signal, which operates in the normal operation mode, FIG. 1b is a detailed circuit diagram of a Yi control block 10 shown in FIG. 1a, and FIG. 1c is a detailed circuit diagram of a pulse control block 20 shown in FIG. 1a. 
The circuit for generating the Yi control signal operating in the normal operation mode includes the Yi control block 10 and the pulse control block 20. The Yi control block 10 logically combines a signal (wlcb) (word line clear bar) and a control signal (sg) (signal having the same path to the signal (wlcb) but having different time delayed by a delay unit 30) to generate the Yi control signal. The pulse control block 20 outputs the Yi control signal as a pulse if the read signal is HIGH or output the Yi control signal as a level if the read signal is LOW.
However, page modes are not available for the conventional circuit shown in FIG. 1. Thus, the conventional circuit shown in FIG. 1 cannot perform a page write mode.